1. Technical Field of the Invention
The present patent relates to a write path scheme in a synchronous dynamic random access memory (DRAM) and, more particularly, to a write path scheme in a DDR II SDRAM.
2. Discussion of Related Art
As a DDR I SDRAM has been replaced with a DDR II SDRAM, new regulations for write latency have been applied in order to increase efficiency of buses. According to the new regulations, column operations are defined on two-clock basis, and specification for interrupt operations is defined not to be stringent.
FIG. 1 is a block diagram showing a conventional write path scheme. Referring to FIG. 1 input data DIN are input to a data input buffer 10 in a serial manner. Such serial input data are latched in a data converter unit which includes first to seventh latches 20 to 80 depending on the rising and the falling edge signals dsrp4 and dsfp4 of a data strobe signal DQS from a DQS buffer 80. Then, four-by-four aligned data (i.e., Algn—dinr0, Algn—dinf0, and Algn—dinr1, Algn—dinf1) are simultaneously input to a Din multiplexer 100 in a parallel manner depending on the rising and the falling edge signals dsrp4 and dsfp4 of the data strobe signal DQS. The Din multiplexer 100 outputs 16, 32, or 64 data din—algn—data to a data input/output sense amplifier 110 depending on X4, X8, or X16 mode. The data input/output sense amplifier 110 is constructed with 64 sense amplifiers, which outputs the data sensed in the data input/output sense amplifier 110 through 64 global input/output lines GIO to a write driver 120 depending on a control signal dinstbp generated from a data input strobe signal generator 90.
The write driver 120 is separately operated depending on X4 and X8 mode selection signals to load input data on local input/output lines LIO and LIOB.
For the conventional write path scheme described above, 64 sense amplifiers in the data input/output sense amplifier unit are arranged to be operated irrespective of X4, X8, or X16 mode, so that 64 global input/output lines are toggled. As a result, since the global input/output lines, which are not used in the X4 or X8 mode, are also toggled, there is a problem with how much power consumption is needed.